1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to electronic fuses in complex integrated circuits that comprise metal gate electrode structures.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with a high performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors and resistors, are typically formed in integrated circuits, as required by the basic circuit layout. Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be improved, but also their packing density may be significantly increased, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SOC).
Although transistor elements are the dominant circuit element in highly complex integrated circuits and substantially determine the overall performance of these devices, other components, such as capacitors, resistors and electronic fuses, also represent essential components, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area. Moreover, the passive circuit elements, such as the resistors, have to be provided with a high degree of accuracy in order to meet tightly set margins according to the basic circuit design. For example, even in substantially digital circuit designs, corresponding resistance values may have to be provided within tightly set tolerance ranges so as to not unduly contribute to operational instabilities and/or enhanced signal propagation delay.
Similarly, electronic fuses may be used in complex integrated circuits as important mechanisms to allow adapting the performance of certain circuit portions to comply with performance of other circuit portions, for instance after completing the manufacturing process and/or during use of the semiconductor device, for instance when certain critical circuit portions may no longer comply with corresponding performance criteria, thereby requiring an adaptation of certain circuit portions, such as re-adjusting an internal voltage supply, thereby re-adjusting overall circuit speed and the like.
For this purpose, the so-called electronic fuses or e-fuses are provided in the semiconductor devices, which represent electronic switches that may be activated once in order to provide a desired circuit adaptation. Hence, the electronic fuses may be considered as having a high impedance state, which typically represents a programmed state, and having a low impedance state, typically representing a non-programmed state of the electronic fuse. Since these electronic fuses may have a significant influence on the overall behavior of the entire integrated circuit, a reliable detection of the non-programmed and the programmed state has to be guaranteed, which is accomplished on the basis of appropriately designed logic circuitry. Furthermore, since typically these electronic fuses may be actuated only once over the lifetime of the semiconductor device under consideration, a corresponding programming activity has to ensure that a desired programmed state of the electronic fuse is reliably generated in order to provide well-defined conditions for the further operational lifetime of the device. The programming of a fuse typically involves the application of a voltage pulse, which in turn induces a current pulse of sufficient current density in order to cause a permanent modification of a specific portion of the fuse. Thus, the electronic behavior of the fuse and the corresponding conductors for supplying the current and voltage to the fuse have to be precisely defined to obtain a reliable programmed state of the fuse. For this purpose, polysilicon is usually used for the fuse bodies, for instance in combination with a metal silicide, in which electromigration effects, in combination with other effects, caused by the current pulse, such as a significant heat generation, may then result in a permanent line degradation, thereby generating a high-ohmic state of the fuse body.
The continuous drive to shrink the feature sizes of complex integrated circuits has resulted in a gate length of field effect transistors of approximately 50 nm and less. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface located between highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, referred to as a channel region, that is disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon forming a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source region and the drain region, which is also referred to as channel length.
Presently, most complex integrated circuits are based on silicon due to the substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and due to the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations. One reason for the important role of silicon for the fabrication of semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows a reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows high temperature processes to be performed, as are typically required for anneal processes in order to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface. Consequently, in field effect transistors, silicon dioxide has been preferably used as a gate insulation layer which separates the gate electrode, frequently comprised of polysilicon, from the silicon channel region. Upon further device scaling, however, the reduction of channel length may require a corresponding adaptation of the thickness of the silicon dioxide gate dielectric in order to substantially avoid a so-called short channel behavior, according to which a variability in channel length may have a significant influence on the resulting threshold voltage of the transistor. Aggressively scaled transistor devices with a relatively low supply voltage, and thus a reduced threshold voltage, therefore, suffer from a significant increase of the leakage current caused by the reduced thickness of a silicon dioxide gate dielectric.
For this reason, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for highly sophisticated applications. Possible alternative materials include such materials that exhibit a significantly higher permittivity, so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide, strontium titanium oxide, hafnium oxide, hafnium silicon oxide, zirconium oxide and the like.
Additionally, transistor performance may further be increased by providing an appropriate conductive material for the gate electrode in order to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface positioned between the gate dielectric material and the polysilicon material, thereby reducing the effective capacitance between the channel region and the gate electrode during transistor operation. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance, while additionally maintaining any leakage currents at an acceptable level. Since the non-polysilicon material, such as titanium nitride and the like, may be formed such that it may be in direct contact with the gate dielectric material, the presence of a depletion zone may thus be avoided, while, at the same time, a moderately high conductivity may be achieved.
As is well known, the threshold voltage of the transistor may depend on the overall transistor configuration, on a complex lateral and vertical dopant profile of the drain and source regions, and the corresponding configuration of the PN junctions, and on the work function of the gate electrode material. Consequently, in addition to providing the desired dopant profiles, the work function of the metal-containing gate electrode material also has to be appropriately adjusted with respect to the conductivity type of the transistor under consideration. For this reason, typically, metal-containing electrode materials may be used for N-channel transistors and P-channel transistors, which may be provided according to well-established manufacturing strategies in a very advanced manufacturing stage. That is, in these approaches, the high-k dielectric material may be formed in combination with an appropriate metal-containing cap layer, such as titanium nitride and the like, followed by the deposition of a polysilicon material, in combination with other materials, if required, which may then be patterned in order to form a gate electrode structure. Concurrently, corresponding resistors may be patterned, as described above. Thereafter, the basic transistor configuration may be completed by forming drain and source regions, performing anneal processes and finally embedding the transistors in a dielectric material. Thereafter, an appropriate process sequence may be performed, in which the top surfaces of the gate electrode structures and all resistive structures, such as fuses, may be exposed and the polysilicon material may be removed. Subsequently, based on a respective masking regime, appropriate metal-containing electrode materials may be filled into gate electrode structures of N-channel transistors and P-channel transistors, respectively, in order to obtain a superior gate structure, including a high-k gate insulating material in combination with a metal-containing electrode material, which may provide an appropriate work function for N-channel transistors and P-channel transistors, respectively. Concurrently, the resistive structures, such as the fuses, may also receive the metal-containing electrode material.
The concept of polysilicon-based electronic fuses in combination with a metal silicide may, thus, no longer be available, which has resulted in the introduction of new approaches for providing electronic fuses in sophisticated semiconductor devices formed on the basis of a replacement gate approach. For example, in some conventional approaches, the active silicon material may be used as an efficient base material for electronic fuses in semiconductor- or silicon-on-insulator (SOI) devices, since crystalline semiconductor material may have similar characteristics in combination with a metal silicide formed therein so as to enable an efficient electromigration effect in the silicon/metal silicide configuration of these electronic fuses. At the same time, the buried insulating material of the SOI configuration may provide a reduced thermal conductivity into the substrate material, thereby providing a desired thermal effect upon programming electronic fuses, since the significant heat generation may represent an important aspect upon permanently “damaging” the fuse body of the semiconductor-based electronic fuse.
In other conventional approaches, the metallization system of the complex semiconductor devices is used as a material system for forming therein metal-based electronic fuses, wherein, typically, a three-dimensional configuration of the electronic fuses may be accomplished by using vias and metal lines in order to generate a desired line degradation on the basis of electromigration. Typically, in sophisticated semiconductor devices, the metallization systems are provided on the basis of a highly conductive metal, such as copper, frequently in combination with sophisticated dielectric materials, such as so-called low-k dielectric materials having a dielectric constant of 3.0 and significantly less. These low-k dielectric materials may typically be provided in the form of porous materials having a reduced mechanical strength due to the reduced density of the material. Owing to the per se desirable high conductivity of the copper material, however, a desired permanent modification of the initial conductivity may require relatively high current densities in the electronic fuse in order to obtain the desired electromigration effect, which may thus result in the desired high ohmic state or programmed state of the electronic fuse. Furthermore, an appropriate generation of heat in and at the electronic fuse may also require reduced cross-sectional areas and/or an increased overall length of the electronic fuse, which may thus result in increased space consumption within the complex metallization system. Moreover, due to the required high current densities, which in turn may require a high current pulse for given lateral dimensions of the vias and metal lines of the electronic fuse, the peripheral circuitry for the electronic fuse, in particular the transistors for providing the programming current pulse, may also have to be provided with increased transistor width, which may thus also contribute to increased area consumption in the device level of the semiconductor device. Additionally, the electromigration of copper in the electronic fuses may result, owing to the reduced mechanical strength and density of the sophisticated dielectric materials, in a significant extrusion of copper material, which may possibly not be efficiently prevented by the standard conductive barrier materials provided in the metal lines and vias of the regular metal features in the metallization system. Since copper readily diffuses in a plurality of dielectric materials, such as silicon dioxide, and, in particular, in low-k dielectric materials, a reliable confinement of copper has to be guaranteed in order to avoid copper migration to sensitive device areas, which may otherwise result in significant modification of the overall device performance or which may even result in a total failure of the semiconductor device. Consequently, additional barrier materials, such as dielectric materials, may have to be provided for sophisticated metal fuses, which may also contribute to additional process complexity.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.